1. Field of the Invention
The following description relates to a semiconductor design technology; and, more particularly, to a nonvolatile memory device including one-time programmable (OTP), unit cell.
2. Description of Related Art
One-time programmable (OTP) unit cells are formed inside a volatile or nonvolatile memory device, such as DRAM, EEPROM or flash memory, and are used for memory repair purpose. In addition, OTP unit cells are used for internal operating voltage and frequency trimming in a mixed-signal chip where an analog chip and a digital chip are mixed.
Generally, each OTP unit cell includes an antifuse implemented with a metal-oxide-semiconductor field effect transistor (MOSFET), which will be referred to as a MOS transistor, and one or more MOS transistors. Such an OTP unit cell is formed inside each memory chip in a single or array configuration and is used for repair or trimming.
FIG. 1 is an equivalent circuit diagram for explaining a conventional nonvolatile memory device including an OTP unit cell.
Referring to FIG. 1, the conventional nonvolatile memory device includes an OTP unit cell 10 and a detecting unit 20. The OTP unit cell 10 includes an antifuse ANT_FS, an n-channel transistor NM1 connected between the antifuse ANT_FS and an output terminal C (an output terminal through which data is outputted in a read operation), and an n-channel transistor NM2 connected between the output terminal C and a fourth input terminal E. The detecting unit 20 is configured with an inverter.
The following description will be made on read and write operations of the conventional nonvolatile memory device.
TABLE 1Terminal (Node)ModeABDECDA_OUTWriteGroundHHHigh——OperationVoltageVoltageReadGroundHHPowerLHOperationVoltageSupplyVoltage
Write Operation
First, a ground voltage is applied to a first input terminal A, and a high voltage is applied to a fourth input terminal E. Also, a signal having a logic level corresponding to a power supply voltage, which will be referred to as a logic high signal hereinafter, is applied to a second input terminal B and a third input terminal D. Accordingly, a gate dielectric breakdown occurs due to a high electric field formed between a substrate and a gate of the antifuse ANT_FS implemented with the MOS transistor. Thus, the gate of the antifuse ANT_FS and the substrate are electrically shorted.
Read Operation
After the write operation, the ground voltage is applied to the first input terminal A, and the power supply voltage is applied to the fourth input terminal E. A logic high signal is inputted to the second input terminal B and the third input terminal D. Accordingly, a current path is formed from the first input terminal A to the fourth input terminal E through the antifuse ANT_FS, the first transistor NM1 and the second transistor NM2. Thus, a logic level corresponding to the ground voltage (hereinafter, referred to as a logic low level) is outputted through the output terminal C.
However, the conventional nonvolatile memory device has the following limitations.
In the conventional nonvolatile memory device, if the antifuse does not stably break down in the read operation and thus the unit cell has high resistance, the detecting unit 20 implemented with the inverter cannot accurately detect the data in the read operation due to a narrow sensing margin of data detected through the output terminal C. Therefore, the inaccurate data detection degrades the reliability in the read operation of the nonvolatile memory device.